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Abstract. This article will discuss the impact on testing of life-cycle costs and present an approach for minimizing
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the overall life-cycle costs of a product by selecting the most economic test strategy at each stage. The selection
of test strategy is based on a detailed economic analysis of the different test techniques available.
Keywords: ECOtest system, life-cycle costs, test methods, test planning.9350
I. Introduction
The economics of testing electronic components,
boards, and systems has long been ignored as a serious
topic for discussion, other than to say, Can we afford
to test? Fortunately, the predominant view today is that
quality is what matters. From this we must conclude
that test is/should be considered essential. There may
still be a wide variety of views as how best to achieve
this, or what level of test is considered sufficient, but
at least the DFT practitioners can raise their heads
above the parapet.
The following statements should put the issues into
context:
i. 70 % of life-cycle costs are determined at the design
stage [1].
ii. >60% of a product's cost can be attributed to test-
ing costs [2].
iii. -50% profits of systems manufacturers comes
from maintenance contracts [3].
Quotes like these, assuming that the test issue is taken
seriously, emphasize that there is a lot of money to be
attributed to test related issues that the designer(s) will
have a direct impact upon.
Of course, there are other factors that have a major
impact upon a product's commercial viability, e.g., time
to market. If the product is too late to the market place,
it doesn't matter what its testability or quality actually
is--no money will be made from it.
It has certainly been the case that designers have not
placed as great an emphasis on testability issues as
perhaps they should have. The reasons for this can be
many: the manager said, "No!"; there was no room
for it; performance impact was too high; or they just
don't know about test... Conversely, even for the test
literate designer the profusion of DFT methods that can
be found in the literature is quite large. Which one(s)
to select? Add to this the fact that the parameters that
are useful in helping to decide the optimum DFT
methods, e.g., circuit size, design time, performance
impact, test pattern generation effort, test length, ATE
requirements etc., all vary with circuit style. Indeed,
it must be said that not using a structured DFT method
at all could be the most cost effective way of achieving
a given level of fault coverage in some circuits.
Unfortunately, the choice of parameters is more than
these already mentioned. When comparing two similar
DFT methods, the problem is compounded somewhat.
Each method will require an overhead in terms of extra
gates, but to differing amounts; they will, hopefully,
increase fault coverage over what might have been