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    A  low level output from Comparator 64 means no prob  lem but if the level therefrom is high when the Counter  59 provides a high window pulse to AND gate 65, the  output of the latter will go high, indicating a printing  error. The error sensed by CPU 70 indicates a failure  which may be caused, for example, by dry print ribbon,  necessitating its replacement.  In conclusion, there has been described a printer kit  which has particular application in the retro?t of exist  ing letter sorting machines. The ability of such ma  chines to selectively operate in a no-print mode, as at  present, or in an automatic print mode, as provided by  the present invention, greatly increases the performance  and usefulness of such machines.  While there have been disclosed speci?c design de  tails applicable to a particular machine, the basic princi  ples taught herein may be applied to other similar ma  chines which nevertheless differ somewhat in construc  tion or operation. Changes and modi?cations of the kit  may be required to suit particular requirements. Such  variations as are within the skill of the designer, and  which do not depart from the true scope and spirit of  the invention are intended to be covered by the follow  ing claims.  We claim:  1. A printer kit for use with a letter sorting machine  having an input console which includes an operator  controlled keyboard for the entry of destination data for  each mail piece and an Expanded ZIP Retro?t (EZR)  for converting such data into a sort bin designation,  comprising in combination:  a printer operatively mounted on said console for  printing coded address information on each mail  piece;  a mode select unit having operator-actuated switch  ing means for selectively placing said console in a  plurality of print and no-print modes;  a console code printer interface coupled between said  printer and said EZR, said console code printer  interface including a main processor and memory,  an I/O data bus controller having an input and an  output terminal coupled to said main processor and  memory, a data path controller having a plurality  of input terminals coupled to said keyboard for  receiving said destination data therefrom and a  plurality of output terminals coupled to said EZR  for providing said last mentioned data thereto, a  keyboard I/O interface unit interposed between  said data path controller and said I/O data bus  controller, said keyboard I/O interface unit having  a plurality of input and output terminals for the  transmission of data between the last mentioned  controllers;  said mode select unit being coupled to said data path  controller for causing the latter to send said desti  nation data directly to said EZR for a no-print  mode and to said I/O data bus controller via said  keyboard I/O interface unit for a print mode, said  mode select unit being further coupled to said I/O  data bus controller whereby said main processor  and memory are conditioned to execute a predeter  mined program stored in the latter in accordance  with the mode select unit; said main processor  accessing said destination data in said I/O data bus  controller, assembling the same and determining  5  15  25  30  35  45  65  8  the code equivalent thereto for printing on said  mail piece, said main processor and memory fur  ther transmitting said keyboard data to said EZR  via said data path controller;  said main processor and memory being comprised of  a CPU, a PROM, and a RAM:  said PROM storing program code and being coupled  in common to said CPU, said I/O data bus control  ler and said RAM via a bidirectional data bus; said  program code comprising modes of console opera  tion selectable in accordance with the switch set‘  ting of said mode select unit, program initialization,  and table lookup for cross referencing destination  data and code to be imprinted on said mail piece;  said CPU being further coupled to said I/O data bus  controller, said PROM and said RAM via a unidi  rectional address bus; said CPU also providing a  R/W signal to said PROM, said RAM and said I/O  data bus controller, means for applying an interrupt  signal to said CPU in response to signals from said  console indicative of an operator-paced or ma  chine-paced print mode, said CPU having ?rst and  second output terminals coupled respectively to  said EZR and said console, said CPU providing a  lookout pulse on said ?rst output terminal for syn  chronizing the destination data transmitted to said  EZR via said data path controller, and a clutch  signal on said second output terminal for synchro  nizing the movement of said mail piece in said  console with the keying of said destination data;  said RAM storing key code information identifying  user-programmable keys present on said keyboard.
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