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摘要在现代集成电路芯片中，随着现代数字电路系统密度和规模的不断扩大，一个系统中通常会包含多个时钟，因此不同时钟之间的数据传输就成为需要解决的问题，而一种可靠易行的解决方案就是异步FIFO。异步FIFO（First In First Out）即先进先出电路，可以在两个不同的时钟系统间进行快速准确的数据传输，是解决异步时钟之间接口电路的一种简便、快捷的方案。异步FIFO在网络接口、数据采集和图像处理等方面得到了十分广泛的应用，由于国内对该方面研究起步较晚，国内的一些研究所和厂商开发的FIFO电路还远不能满足市场和军事需求。23606
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本毕业设计课题任务以Quartus II作为FPGA的开发环境，利用VHDL 硬件描述语言进行逻辑描述，采用层次化、描述语言和图形输入相结合的方法设计了一个64×8位的异步FIFO电路。首先利用VHDL 硬件描述语言进行逻辑描述，编写实现异步FIFO各功能模块程序；其次通过层次化、描述语言和图形输入相结合的方法将各模块整合为异步FIFO顶层模块，使电路具有满、半满、空及复位标志位逻辑产生功能，并通过Quartus II软件的波形编辑器对其进行时序仿真和分析。
关键词：异步FIFO FPGA VHDL语言 Quartus II
毕业设计说明书（毕业论文）外文摘要
Title Design of Asynchronous FIFO based on FPGA
Abstract
In modern integrated circuit chip, with the continuous expansion of modern digital circuit density and size of the system , a system often contain multiple clock , so data transfer between different clock becomes the problem to be solved , but a reliable and easy line solution is asynchronous FIFO. Asynchronous FIFO (First In First Out) FIFO circuit that allows fast and accurate data transfer between two different clock system is to solve the interface circuit between asynchronous clock of a simple, quick solution. Asynchronous FIFO in the network interface , data acquisition and image processing has been very widely used, due to the late start of the domestic research in this regard , some domestic research institutes and manufacturers to develop the FIFO circuit also can not meet the needs of the market and the military .
The graduation project tasks as Quartus II FPGA development environment , the use of VHDL hardware description language for logical descriptions , using hierarchical , language and graphical input method combining describe the design of a 64 × 8 -bit asynchronous FIFO circuit . First, the use of VHDL hardware description language for logical descriptions , write asynchronous FIFO realize the function module program ; followed by hierarchical description language and graphical input method combining asynchronous FIFO modules integrated into the top module , the circuit has a full, half full , empty and reset the flag logic generating function , and its timing simulation and analysis by the Quartus II software waveform editor.
Keywords asynchronous FIFO FPGA VHDL Quartus II
目 次
1 绪论.1
1.1 本课题研究背景及意义1
1.2 国内外相关技术发展现状 1
1.3 论文的主要内容及章节安排 2
2 异步FIFO设计要求及设计方案 .3
2.1 异步FIFO设计要求 .3
2.2 异步FIFO基本原理 . 3
2.3 异步FIFO设计难点 . 5
2.4 异步FIFO系统设计方案 5
2.5 异步FIFO验证方案. .6
3 模块设计与实现 8
3.1格雷码计数器模块.8
3.2格雷码/二进制码转换模块11
3.3同步寄存器模块.13
3.4空满标志产生模块.14
3.5双端口RAM .19
3.6 模块整合 . 20
4 时序仿真与实现.22
4.1 时序仿真及功能测试 . 22
4.2 时序仿真结果总结 24
结 论 26
致 谢 .27
参 考 文 献 28